The present invention relates to a circuit for performing a predetermined logical function, and more particularly to a logic circuit which includes a plurality of logic elements comprised of depletion-mode field-effect transistors.
GaAs integrated-circuit fabrication technology has recently been developed. This technology has GaAs Schottky gate field-effect transistors (also known as an MESFET) and has developed the fabrication of digital IC for performing a predetermined logical function. Since the carrier mobility of GaAs substrate material was larger than that of Si substrate material, the above-mentioned digital IC could have carried out the logical function at an ultrahigh speed. It has been well known by those skilled in the art that a digital IC including a depletion-mode FET (also known as a normally-on type FET) has operated further at an ultrahigh speed. In the IEEE Journal of Solid-State Circuits, vol. SC-13, No. 4, August 1978 of FIG. 6 on page 423, a 4-input NOR-circuit employing a Schottky diode-FET logic (SDFL) circuit was disclosed.
However, the logic circuits comprised of the above-mentioned depletion-mode FETs have required two types of power source voltages, e.g., positive and negative voltages in operation. In other words, when the above-mentioned digital IC has been associated in a predetermined circuit arrangement for use, it has been designed to produce at least two types of power voltages for the above-mentioned IC. As a result, it had such disadvantages that the circuit of the connection of the power source has undesirably been complicated and the compact containment of the entire device has been prevented.
As a logic circuit which has solved the above-mentioned problems, there is a logic circuit called "a direct coupled FET logic (DCFL)", for example. This circuit is comprised of depletion-mode FETs serving as active loads and enhancement-mode FETs functioning as switching transistors. The enhancement-mode FETs connected commonly at the source electrode to each other have drain electrodes connected through the active loads to one positive potential power source voltage. At this time the source electrodes are grounded. Further, the drain electrode of one switching transistor is connected to the gate electrode of the switching transistor in the next stage. According to such circuit arrangement, forward voltage is applied between the gate and source electrodes of the enhancement-mode FETs as switching transistors. Thus, the gate potential of the switching FETs is clamped to the forward voltage (approx. 0.8 V) of Schottky. Therefore, the logic amplitude of the switching transistors has allowed narrow (e.g., reduced to 0.6 V) variation. As a consequence, the prior art logic circuit has such disadvantages that the noise margin voltage of the logic circuit is low and the noise resistance characteristics is deteriorated. When the above logic circuit is integrated in large scale or very large scale to be formed on one chip, the reduction of such noise margin voltage has been undesirably promoted, since the variation of the noise margin voltage of the switching transistors caused by the difference of the threshold voltage irregularity and/or fan out/in number should be further considered.